1. Technical Field
This invention generally relates to computer memory systems, and more specifically relates to a memory controller for a computer system.
2. Background Art
In a closed memory subsystem of a computer data system, data may be accessed by a variety of units over a common memory bus. Security of data is such a system can be a concern. Mechanisms to encrypt data have been used but always at the sacrifice of performance. Depending on the encryption scheme used, the latency and performance degradation of data transfer through that unit can be substantial.
Prior art solutions do not address the concerns of both performance and data protection. The prior art memory controller systems either provide controls to maintain security of the data or they control performance on the interface, but not both. Performance degradation caused by security encryption and decryption by one unit on the bus can lead to more serious performance bottlenecks as other logic units on the bus are delayed access to memory.
Without a means for securing data while maintaining preferred performance characteristics, by regulating the security controls based on performance parameters collected on the interface to memory, computer systems will be required to trade off security and performance in a memory system.